Title:
METAL WIRING PACKAGE LEVEL TEST PATTERN OF SEMICONDUCTOR ELEMENT AND TESTING METHOD
Document Type and Number:
Japanese Patent JP3741885
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To accurately perform the EM(electromigration) evaluation of metal wiring by completely preventing temperature gradient due to Joule heat on testing.
SOLUTION: The metal wiring package level test pattern of a semiconductor element is connected to a test line 24 for testing and both terminals of the test line 24, and is provided with a current supply pad 21 for supplying current to the test line 24, a voltage-sensing region 26 that is located at both terminals of the test line 24 and senses the voltage of the test line 24, and a heating region 23 for varying the temperature of the current supply pad 21.
Inventors:
Ikan Yor
Application Number:
JP36447498A
Publication Date:
February 01, 2006
Filing Date:
December 22, 1998
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G01N27/00; H01L21/66; G01R31/28; H01L23/544; (IPC1-7): G01N27/00
Domestic Patent References:
| JP7130816A | ||||
| JP7066201A |
Attorney, Agent or Firm:
Hironobu Onda