Title:
METALLIC INSULATOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5837964
Kind Code:
A
Abstract:
A metal insulator semiconductor device comprises a semiconductor substrate (1, 15) having input and output terminals (2, 3, 79, 16, 17, 23, 24) with at least one gate (8, 20, 22) arranged on an insulating layer between the two terminals. In this invention the insulator under the gate is formed as a double layer (4, 5); the first layer (4, 18) next to the substrate, is thin e.g. less than 250 ANGSTROM whilst the second layer (5, 19) is thicker e.g. more than 350 ANGSTROM thick. One layer is accumulating whilst the other is depleting. The amount of band bending at the substrate insulator interface is controlled by the thickness of the first layer (4, 18). Substrate materials include CDxHg1-xTe, Si, InP, GaAs, GaAlAs. The first layer (4, 18) may be of anodic oxide. The second layer (5, 19) may be ZnS. Field effect transducers and charge coupled devices may be made incorporating the double layer gate insulator.
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Inventors:
ANSONII BURAIAN DEIIN
ANSONII MAIKERU HOWAITO
ANSONII MAIKERU HOWAITO
Application Number:
JP11382382A
Publication Date:
March 05, 1983
Filing Date:
June 30, 1982
Export Citation:
Assignee:
SECR DEFENCE BRIT
International Classes:
H01L21/28; H01L21/336; H01L21/339; H01L21/34; H01L21/44; H01L29/20; H01L29/221; H01L29/51; H01L29/762; H01L29/78; (IPC1-7): H01L29/76; H01L29/78
Attorney, Agent or Firm:
Yoshio Kawaguchi