Title:
METHOD FOR ADJUSTING POWER CONSUMPTION AND SYSTEM THEREFOR
Document Type and Number:
Japanese Patent JP3963492
Kind Code:
B2
Abstract:
PURPOSE: To provide an improved method and device for reducing power consumption in an integrated circuit device.
CONSTITUTION: A clock rate for a device is controlled by using an integrated circuit responding to a device temperature. Then, a frequency control circuit 40 (which is constituted of a temperature comparator circuit 30, update signal 34, and up/down counter 22) which changes the clock rate of the device according as the device temperature changes is added to the integrated circuit. Thus, the device clock rate is adjusted by the temperature of the device. The means which operates the adjustment can be updated, and the update can be attained by delaying the operation of the clock rate generated inside by a voltage control oscillator or a phase lock loop(PLL) or the like, or digitally standardizing an outside clock input.
Inventors:
Brian Kay. Herbert
Application Number:
JP11543495A
Publication Date:
August 22, 2007
Filing Date:
May 15, 1995
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
G06F1/04; G06F1/20; G06F1/32; H02H5/04; H03L1/02; H03L7/08; H03L7/18; (IPC1-7): G06F1/04; G06F1/32
Domestic Patent References:
| JP2083720A |
Attorney, Agent or Firm:
Yoshiaki Nishiyama
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