To calculate a yield which is extremely close to the yield of an actual product at a high speed even for a complicated pattern of a highly integrated LSI.
An object region for which a critical area in pattern layout data is calculated is chosen. A first rectangular region having a width which is equal to or larger than the minimum width Xmin of the object region and smaller than X1 which is the sum of Xmin and an incremental width ΔX is extracted from the object region. After the total area S1 of the first rectangular region is derived, the first rectangular region is excluded from the object region. Successively, an (n+1)th rectangular region having a width which is equal to or larger than Xn (n is a natural number) and smaller than Xn+1 which is the sum of Xn and the incremental width ΔX is extracted from the object region, and the total area Sn+1 of the (n+1)th rectangular region is derived. A process by which the (n+1)th rectangular region is excluded from the object region is repeated until Xn reaches a prescribed value Xt increasing n one by one from 1 to t. Subsequently, the critical area is calculated using the calculated total areas.
ITO MITSUSANE
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori