Title:
動的仮想システム・オン・チップのための方法および装置
Document Type and Number:
Japanese Patent JP7334396
Kind Code:
B2
Abstract:
A processor device comprises a plurality of virtual systems on chip, configured to utilize resources of a plurality of resources in accordance with a resource alignment between the plurality of virtual systems on chip and the plurality of resources. The processor device may further comprises a resource aligning unit configured to modify the resource alignment, dynamically, responsive to at least one event. Modifying the resource alignment, dynamically, may prevent a loss in throughput otherwise effectuated by the at least one event.
Inventors:
Goial Rajan
Hussain Muhammad Rajib
Kessler Richard Yee
Hussain Muhammad Rajib
Kessler Richard Yee
Application Number:
JP2022094870A
Publication Date:
August 29, 2023
Filing Date:
June 13, 2022
Export Citation:
Assignee:
Marvel Asia PTE, Limited
International Classes:
G06F9/50; G06F9/455
Domestic Patent References:
| JP2013257789A | ||||
| JP2015529918A | ||||
| JP2015510201A | ||||
| JP2016509412A | ||||
| JP2015204614A |
Foreign References:
| US20110271277 | ||||
| US20160092677 | ||||
| WO2015178032A1 |
Attorney, Agent or Firm:
Patent Attorney Corporation RYUKA International Patent Office
Previous Patent: Video classification methods, devices, equipment and storage media
Next Patent: DELETED FILE MANAGING SYSTEM
Next Patent: DELETED FILE MANAGING SYSTEM