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Patent Searching and Data


Title:
METHOD AND APPARATUS FOR FAILURE DIAGNOSIS OF LOGIC INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH02105437
Kind Code:
A
Abstract:

PURPOSE: To diagnose a fixed failure such as a short circuit, a disconnection or the like and a transient failure such as a delay without a need for a failure dictionary and a special test circuit by a method wherein an operating waveform of an integrated circuit is observed by using an electron beam tester and this observed waveform is compared with an expected waveform formed by a simulation.

CONSTITUTION: A test pattern is input to an input terminal of an integrated circuit to be diagnosed; this observed waveform is compared with an expected waveform by a logical simulation; when they do not coincide, a flip-flop(FF) to which this signal is coupled by using this disagreement as a malfunction output terminal is found from a logical connection file; this output signal is observed by using a noncontact tester 4; this observation is compared with an expected waveform; the FF of the disagreement is regarded as a malfunction FF; in addition, its input source FF is checked; the malfunction FF is found. Then, a malfunction about an input signal of a gate circuit connected directly to this input signal is found; a failure part is detected.


Inventors:
YAMAGUCHI NOBORU
SATO TSUKASA
HAGIWARA YOSHIMUNE
Application Number:
JP25695488A
Publication Date:
April 18, 1990
Filing Date:
October 14, 1988
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G01R31/302; H01L21/66; H01L21/82; G01R31/317; (IPC1-7): G01R31/302; G01R31/318; H01L21/66; H01L21/82
Attorney, Agent or Firm:
Junnosuke Nakamura