Title:
METHOD AND APPARATUS FOR IDENTIFYING PULLING-OUT OF SYNCHRONISM FOR TWO WORD SEQUENCES
Document Type and Number:
Japanese Patent JPH05102951
Kind Code:
A
Abstract:
PURPOSE: To provide a method for identifying out of synchronism between two sets of word sequence where re-synchronization of a reference pattern signal is not usually started on the occurrence of a burst error. CONSTITUTION: An output signal of an EXOR circuit 3 denotes an error signal SF1, and a momentary bit sequence of the error signal and a bit sequence FS2 resulting from deviating the bit sequence SF1 timewise by one period time of a reference signal RS are compared and when the momentary bit sequence FS1 is coincident with the bit sequence FS2 obtained by deviating the bit sequence FS1 by one period time, re-synchronization of the reference signal RS is started.
Inventors:
GIYUNTAA RENTSU
Application Number:
JP8386092A
Publication Date:
April 23, 1993
Filing Date:
April 06, 1992
Export Citation:
Assignee:
WANDEL & GOLTERMANN
International Classes:
H04L7/00; H04L1/24; H04L7/04; (IPC1-7): H04L7/00
Domestic Patent References:
| JPS6178239A | 1986-04-21 | |||
| JPS5214303A | 1977-02-03 | |||
| JPH03274836A | 1991-12-05 |
Attorney, Agent or Firm:
Toshio Yano (2 outside)
Previous Patent: アミド化合物の還元によるアミン化合物の製造方法
Next Patent: CLOCK SWITCHING CIRCUIT FOR DIGITAL TRANSMISSION DEVICE
Next Patent: CLOCK SWITCHING CIRCUIT FOR DIGITAL TRANSMISSION DEVICE