To provide a high performance pulse width modulated (PWM) circuit to be mounted on an IC.

This PWM circuit (100) comprises a selective synchronization circuit (108) for receiving timing command signals (106), selectively changing the phase of at least one of the timing signals, and outputting corresponding synchronous timing signals (112) including the timing signal with the phase changed. A tap selection circuit (114) receives the synchronous timing signals and outputs selected timing signals (120) logically coupled by a transition producing circuit (122) for producing PWM output signals (124) based on transition in the selected timing signals. A clock delay circuit (116) receives main clock signals and supplies concerning tap signals (118) to the tap selection circuit (114). Each of the tap signals is individually delayed expression of the main clock signals, to be used in the tap selection circuit (114) for controlling the outputting operation for each selected timing signal.