Title:
METHOD FOR APPLYING HIGH SPEED FREQUENCY-DIVISION
Document Type and Number:
Japanese Patent JP2016129342
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a frequency divider capable of operating at a high speed, and a phase-locked loop.SOLUTION: A frequency divider 200 includes: a lowest significant (LS) step 220; a plurality of divider steps 230-1 to 230-N which is cascaded; and an output step 210. The LS step 220 receives an input signal 201, a program bit, and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider steps 230-1 to 230-N is frequency-divided a frequency of the output in the step just before by a value specified by the corresponding program bit and the corresponding mode signal. The output step 210 receives the output mode signal and a control signal, and generate an output signal 299 by frequency-dividing the frequency of the output mode signal with two in the case where a logical level of the control signal is equal 1. In the other case, the output step does not frequency-divide and transmits the output signal.SELECTED DRAWING: Figure 2
Inventors:
KARTHIK SUBBURAJ
DHANYA K
DHANYA K
Application Number:
JP2016012285A
Publication Date:
July 14, 2016
Filing Date:
January 26, 2016
Export Citation:
Assignee:
TEXAS INSTRUMENTS JAPAN
TEXAS INSTRUMENTS INC
TEXAS INSTRUMENTS INC
International Classes:
H03K23/64; H03K23/00; H03K27/00; H03L7/08
Domestic Patent References:
| JPH03136520A | 1991-06-11 | |||
| JPH04117816A | 1992-04-17 | |||
| JP2005508577A | 2005-03-31 |
Foreign References:
| WO2010022366A1 | 2010-02-25 | |||
| US20050058236A1 | 2005-03-17 |
Attorney, Agent or Firm:
Kyozo Katayose
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