Title:
METHOD OF BIASING NONVOLATILE FLASH-EEPROM MEMORY ARRAY
Document Type and Number:
Japanese Patent JP3553121
Kind Code:
B2
Abstract:
PURPOSE: To prevent the occurrences of stress in the drain terminal of an unselected memory cell in a selected bit line by biasing a positive voltage with respect to the drain terminal of the unselected memory cell for a substrate region and by making the source terminal remain floating.
CONSTITUTION: This memory array is provided with a drain region 29 arranged into rows and columns and connected to each of bit lines BL, a source region 30 connected to each source line 24, a control gate region connected to each word line WL, and a large number of memory cells 21 each having a substrate region 28 housing the drain and source regions. A drain terminal of an unselected memory cell, which is connected to a selected bit line during a reading step but not connected to the selected word line and is not connected to the source terminal of the selected memory cell, is biased with a positive voltage with respect to the substrate region 28. The source terminal is kept floating.
Inventors:
Giovanni Campard
Giuseppe Chrisenza
Marco dalla Bora
Giuseppe Chrisenza
Marco dalla Bora
Application Number:
JP4720994A
Publication Date:
August 11, 2004
Filing Date:
March 17, 1994
Export Citation:
Assignee:
SGS-THOMSON MICROELECTRO NICS S.R.L.
International Classes:
G11C17/00; G11C16/04; G11C16/06; G11C16/30; H01L21/8247; H01L27/115; (IPC1-7): H01L21/8247; G11C16/04; G11C16/06; H01L27/115
Domestic Patent References:
| JP5110113A | ||||
| JP6477160A |
Foreign References:
| DE4213741A1 |
Attorney, Agent or Firm:
Michiteru Soga
Yoshio Kobayashi
Yutaka Ikeya
Hidetoshi Furukawa
Suzuki Kenchi
Masahisa Hase
Tetsuo Kuroiwa
Yoshio Kobayashi
Yutaka Ikeya
Hidetoshi Furukawa
Suzuki Kenchi
Masahisa Hase
Tetsuo Kuroiwa