Title:
METHOD AND BOARD FOR INSPECTING FLIP-CHIP IC
Document Type and Number:
Japanese Patent JP3050172
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To ensure electrical connection of a flip-chip IC and a board by forming solder bump connection pad parts on a board in same pattern as the solder bumps of a semiconductor device while projecting above the surface of a thin film on the board.
SOLUTION: Solder bump connection pad parts 7 of a conductive metal material are formed on the ceramic multilayer wiring board of an inspection board 3 in same pattern as the solder bumps 2 formed on a semiconductor TC 1 while projecting about 30 μm above an insulating organic thin film 6. The semiconductor IC 1 is positioned on the inspection board 3 and mounted thereon in the atmosphere of inert gas, or the like, by IR reflow, or the like. The solder bump 2 on the semiconductor IC 1 is wetted surely to the connection pad part 7 to form an intermetallic compound thus providing a stabilized electric connection between the semiconductor IC 1 and the inspection board 3. Subsequently, an inspection probe 5 touches a probe contact inspection pad 4b to inspect the electrical characteristics of the semiconductor IC.
Inventors:
Hirokazu Honda
Application Number:
JP18770997A
Publication Date:
June 12, 2000
Filing Date:
June 27, 1997
Export Citation:
Assignee:
NEC
International Classes:
H01L21/60; H01L21/66; G01R31/26; H05K3/28; H05K3/34; H05K3/40; (IPC1-7): G01R31/26; H01L21/66
Domestic Patent References:
| JP9113578A | ||||
| JP8297142A | ||||
| JP8304459A |
Attorney, Agent or Firm:
Asamichi Kato