Title:
METHOD FOR CALCULATING DEGREE OF FREEDOM OF LOGIC FUNCTION MAPPED TO LUT TYPE FPGA AND METHOD FOR OPTIMIZING CIRCUIT WHILE USING DEGREE OF FREEDOM
Document Type and Number:
Japanese Patent JP3412731
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To express much higher degree of freedom of a logic function by calculating the degree of freedom of the logic function while expressing it as the cluster of paired logic functions.
SOLUTION: A device reads circuit diagram data mapped from another function block to a look-up table(LUT) type field programmable gate array(FPGA) stored in a storage device 11, calculates the degree of freedom of the logic function in that circuit through a calculation part 13 and stores the result in a storage device 15, and this result is to be used by another function block 17. Then, on the condition that an external logic is not to be changed, while considering that the internal logic of an LUT can be freely changed, the degree of freedom of the logic function expressed by the LUT in the circuit or the connection between the LUT is calculated, by expressing it as the cluster of paired logic functions to be distinguished at least when this logic function becomes '1' or '0'.
Inventors:
Shigeru Yamashita
Hiroshi Sawada
Akira Nagoya
Hiroshi Sawada
Akira Nagoya
Application Number:
JP11377496A
Publication Date:
June 03, 2003
Filing Date:
May 08, 1996
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP8292969A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)