Title:
METHOD AND CIRCUIT FOR CONVERTING DATA OUTPUT ORDER IN INVERSE DISCRETE COSINE TRANSFORMER
Document Type and Number:
Japanese Patent JPH09219862
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To eliminate the need of a format converter and to simplify a succeeding process by matching the orders of image signals outputted from an inverse discrete cosine transformer and the image signals outputted from a motion compensation part by an address mapping system. SOLUTION: By the address mapping system, the output terminal of a write control part 41 is respectively connected to the input terminals of a read control part 43 and a memory 45. In this case, in an external request processing part, request signals outputted from the write control part 41 are received and acceptance signals are generated and impressed to the read control part 43. When the impressed signals IDCT-FIFO read start are inputted to the read control part 43, a read count is increased one by one and a write operation is started. Since such a write operation and a read operation are simultaneously performed, by performing the read operation in the 'high' section of CIK 20 which is a system clock and performing the write operation in a 'low' section, the overall timing chart is constituted. Also, successively generated read addresses are respectively read corresponding to the mode of input data.
Inventors:
CHIN DAIIN
Application Number:
JP32715896A
Publication Date:
August 19, 1997
Filing Date:
December 06, 1996
Export Citation:
Assignee:
SAMSUNG ELECTRONIC
International Classes:
H04N5/92; G06F17/14; G06T9/00; H03M7/30; H03M7/38; H04N7/24; H04N19/42; H04N19/423; H04N19/503; H04N19/60; H04N19/61; H04N19/625; H04N19/85; (IPC1-7): H04N7/30; H03M7/30; H03M7/38; H04N5/92
Attorney, Agent or Firm:
Tadahiko Ito (1 outside)
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