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Patent Searching and Data


Title:
METHOD AND CIRCUIT FOR DECIDING LEAD/LAG OF INTER-CHANNEL PHASE
Document Type and Number:
Japanese Patent JPH08181687
Kind Code:
A
Abstract:

PURPOSE: To decide lead/lag in a short time while reducing a circuit scale by deciding the lead/lag of inter-channel phase through the comparison of a frame number when two or more channels are used to send data.

CONSTITUTION: A phase decision reference output circuit 2 provides an output of a phase decision reference value A. A frame number output circuit 4 outputs a frame number M of a frame received via a 1st channel and a frame number N of a frame received via a 2nd channel. A 1st circuit 6 outputs an absolute value D of a reference value A-number N and a code signal of the absolute value D. A 2nd circuit 8 obtains a frame number M + absolute value D = correction value P when the sign of the absolute value D indicates a positive value and outputs a frame number M-absolute value D = correction value P when the sign of the absolute value D indicates a negative value. A decision circuit 10 decides that a frame of the 1st channel is advanced in the case of correction value P > reference value A and that a frame of the 2nd channel is advanced in the case of correction value P < reference value A.


Inventors:
MAEHIRA MASAYUKI
Application Number:
JP31869594A
Publication Date:
July 12, 1996
Filing Date:
December 21, 1994
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L7/02; H04L7/00; H04L7/08; (IPC1-7): H04L7/02; H04L7/08
Attorney, Agent or Firm:
Furuya Fumio (1 person outside)