To provide a system and method for efficiently processing multiple cache misses in a command queue.
Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in the command queue while handling multiple translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs while an outstanding miss is being handled, the pipeline may be stalled and the command causing the second miss and all subsequent commands may be processed again after the first miss is handled.
COPYRIGHT: (C)2007,JPO&INPIT
IRISH JOHN DAVID
CHAD B MCBRIDE
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi