Title:
METHOD OF CONCEALING PACKET LOSS IN ADPCM CODEC AND ADPCM DECODER WITH PLC CIRCUIT
Document Type and Number:
Japanese Patent JP2016105168
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a method of concealing packet loss in ADPCM codec, and an ADPCM decoder with a PLC circuit.SOLUTION: The present invention relates to a method of concealing packet loss in ADPCM codec as well as to an ADPCM decoder with a PLC circuit. The method is characterized in that, in a predetermined transition period between a correction signal (x) and substitute signal (x) supplied by the PLC circuit, difference ((d) between the substitute signal (x) and a computed prediction signal (x) in each subband is combined with a dequantized prediction error (d) to receive a dequantized combined prediction error (d) which is added to the prediction signal (x) to obtain a combined transition signal (x) which is used to serve as a reference for an output signal (x=x) during the transition period as well as to adapt all decoder parameters.SELECTED DRAWING: Figure 3
Inventors:
MARKUS ZAUNSCHIRM
PAOLO CASTIGLIONE
PAOLO CASTIGLIONE
Application Number:
JP2015227409A
Publication Date:
June 09, 2016
Filing Date:
November 20, 2015
Export Citation:
Assignee:
AKG ACOUSTICS GMBH
International Classes:
G10L19/005; G10L19/00; H03M7/38
Attorney, Agent or Firm:
Hidesaku Yamamoto
Natsuki Morishita
Takatoshi Iida
Daisuke Ishikawa
Kensaku Yamamoto
Natsuki Morishita
Takatoshi Iida
Daisuke Ishikawa
Kensaku Yamamoto
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