To provide a method of control for a delay locked loop which generates a stable clock, a semiconductor device including the delay locked loop and a system which is operated by the clock synchronization.

With respect to the delay locked loop(DLL), a gray code counter (gray code: alternation code) is used as a delay register. In this way, hops of the delay time (discontinuous hops) can be minimized by putting up always only one bit of carry even if a metastable state occurs.