PURPOSE: To reduce remarkably the overhead at mis-hit of a cache memory in the store-in system by eliminating an unnecessary block transfer from a main memory to the cache memory when the cache memory is subject to mis-hit at consecutive write access.

CONSTITUTION: When a read/write access to a memory is discriminated to be write, whether or not a BLK bit is 1 is checked, and when this is 1, that is, a bit representing that the said write access is one of write accesses executed consecutively for one block's content, is 1, whether or not the present write access is an access to the head address of the corresponding block is checked. When so, a data is written in the corresponding block of the cache memory. Succeedingly a D-bit is set, the content of the directory of the selected side so that the access consecutive for one block's content is applied to the same block in the cache, a V-bit is set and a reply is returned to the access sender.