To provide a frequency divider circuit for reducing power consumption and facilitating timing and a PLL provided with the frequency divider circuit.

This PLL is provided with a phase comparator circuit 103 for inputting a reference clock to one input port, a charge pump 104 for generating voltage corresponding to a phase difference outputted from the phase comparator circuit, a loop filter 105 for filtering, a voltage-controlled oscillator 106, the frequency divider circuit 107 for receiving the output clock of the voltage-controlled oscillator as an input and performing P frequency division of the frequency of the output clock, an A counter 109 for performing A frequency division of a P frequency division output of the frequency divider circuit, circuits 121 and 122 for generating two signals with a phase difference corresponding to one cycle of the P frequency division output of the frequency divider circuit 107 in every A frequency division in the A counter 109 and an interpolator 123. The interpolator 123 is provided with an arithmetic circuit 110 and a control circuit 130 for controlling operation timing of the interpolator 123 and outputting a signal for controlling an internal division ratio B, and an output is inputted to the phase comparator circuit 103, the phase of the output is compared with that of a reference clock to realize frequency division of the number of divisions N=A×P+B.