Title:
METHOD FOR CONTROLLING CLOCK SIGNAL AND ITS DEVICE
Document Type and Number:
Japanese Patent JP3220052
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a clock signal control method and its device where high speed property is realized and also which are used as a variable delay circuit.
SOLUTION: Data of a multiplying number deciding code 12 and an external clock 7 are inputted from the outside, the operation range of a multi-phase clock multiplying circuit 2 is adjusted by a control signal 11 from a frequency detecting circuit 6, a multi-phase clock 8 obtained by frequency-dividing the external clock by a frequency divider 1 is inputted to the multi-phase multiplying circuit 2, a clock pulse is divided into N-number phase clocks 9 in a number which is designated by the multiplying number deciding code 12 and, moreover, synthesization is executed in a clock synthesizing circuit 5 so that a multiplying clock 10 is outputted.
Inventors:
Takanori Saeki
Application Number:
JP15704297A
Publication Date:
October 22, 2001
Filing Date:
June 13, 1997
Export Citation:
Assignee:
NEC
International Classes:
H03K5/00; G06F1/06; H03K5/13; (IPC1-7): H03K5/00
Domestic Patent References:
| JP1152815A | ||||
| JP7321613A | ||||
| JP4277921A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)