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Patent Searching and Data


Title:
METHOD FOR CONTROLLING MEMORY ADDRESS SPECIFICATION
Document Type and Number:
Japanese Patent JPS59180617
Kind Code:
A
Abstract:

PURPOSE: To improve the using efficiency of a memory space by forming a storage address specifying table specifying an address space storing the information volume of each I/O apparatus in a memory of a computer.

CONSTITUTION: The storage address specifying table previously stored in a memory of a CPU6 in a computer 1 is sent to a DMAIF11 in an IF device 3 through a DMA interface IF8 and read in a memory in an arithmetic unit MPU9 through a bus 13 to process information from the I/O apparatus 2. When the information from the I/O apparatus 2 is inputted to the MPU9 through an apparatus IF12 under said status, the I/O apparatus sending the information is decided and the storage address specifying table is retrieved to specify the specification address. Subsequently, the inputted information is stored in a memory address in the CPU6 which corresponds to the specification address. Thus, the information in the apparatus 2 is stored in the specified minimum memory space in accordance with each maximum information volume of each master or local station.


Inventors:
DOUYA RIYOUJI
Application Number:
JP5388683A
Publication Date:
October 13, 1984
Filing Date:
March 31, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
G06F3/00; (IPC1-7): G06F3/00
Attorney, Agent or Firm:
Yoshiaki Inomata