To obtain a method for designing an integrated circuit with reduced EMI(electromagnetic interference) in which circuit clock shew is offset so as to secure a holding margin.

This integrated circuit is provided, on or automatic arrangement and wiring program, with clock driver cells c and d and FF(flip-flop) f and g, the input stages of which delay elements are connected with and which are equivalent to a clock driver cell b or FF e with which no delay element is connected as a cell library. After the automatic arrangement and writing processing is operated, the b is replaced by the c or d, and the e is replaced by the f or g.