To make the processing time possible to be as short as possible.

This designing method is provided with a step for performing a timing analysis on the basis of real wiring information after a layout, cell information and chip information, a step for deciding the existence/absence of timing violation locations, and a step for finishing the timing analysis when the timing violation locations do not exist, correcting the violation locations when any violation location exist, subsequently calculating the wiring information of the corrected locations on the basis of the real wiring information, and performing a layout again to return to the step for performing the timing analysis.