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Patent Searching and Data


Title:
METHOD FOR DESIGNING MICROPROCESSOR SOFTWARE CORE WITH VARIABLE HARDWARE SCALE
Document Type and Number:
Japanese Patent JPH10326291
Kind Code:
A
Abstract:

To eliminate H/W blocks which are unnecessary for software(S/W) processing for a microprocessor (μP) by determining a hardware(H/W) subelement obtained and determining a scale when the total time needed to execute decomposed microcodes is equal to or shorter than a software(S/W) process upper-limit time.

The clock period of a μP software core is given as information (step S3) and the execution processing time obtained from the number of S/W program processing steps is compared with a system request performance (step S5). When the processing tine has margin for system request performance, a microcode which performs other equivalent processes using no exclusive H/W block is substituted for (step S6). A system processing time, on the other hand, is calculated (step S14) and compared with a system processing restriction time (step S15). When the system processing restriction time is not exceeded and the processing can be performed, a multiplier is unnecessary finally and the area reduction of the μP software core is determined (step S17).


Inventors:
OTSUJI AKIO
Application Number:
JP13313397A
Publication Date:
December 08, 1998
Filing Date:
May 23, 1997
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Attorney, Agent or Firm:
Kaneo Miyata (2 outside)