Title:
半導体装置の良否判定方法
Document Type and Number:
Japanese Patent JP7372104
Kind Code:
B2
Abstract:
To determine the quality of formation of a structure for ensuring the withstanding pressure of a semiconductor device including a resistance chip.SOLUTION: The present invention relates to a method for determining the quality of a semiconductor device formed by attaching a resistance chip 130 to a die pad 160 by a dielectric member 150, the resistance chip being formed by arranging a division resistance element 133 on the upper surface of an insulating layer 132 on an upper surface of a semiconductor substrate 131. The quality of the semiconductor device is determined by observing the waveform of a leakage current IL flowing in the die pad 160 from the division resistance element 133 when an AC high voltage Vt is applied.SELECTED DRAWING: Figure 2
More Like This:
| JP5128512 | Burn-in device |
| JPS5648721 | INTEGRATED CIRCUIT |
| WO/2017/007200 | TEST SOCKET, TEST SOCKET MANUFACTURING METHOD, AND JIG ASSEMBLY FOR TEST SOCKET |
Inventors:
Daisuke Hirano
Yuya Ohashi
Yuya Ohashi
Application Number:
JP2019184940A
Publication Date:
October 31, 2023
Filing Date:
October 08, 2019
Export Citation:
Assignee:
Nisshinbo Microdevices Inc.
International Classes:
G01R31/26; G01R31/00; G01R31/18; G01R31/52
Domestic Patent References:
| JP2019102725A | ||||
| JP2004271245A | ||||
| JP2011252792A | ||||
| JP2016136608A |
Foreign References:
| WO2010122889A1 |
Attorney, Agent or Firm:
Sakai International Patent Office
Previous Patent: Silicate nanosheet dispersion and its manufacturing method
Next Patent: lighting equipment
Next Patent: lighting equipment