PURPOSE: To prevent an existing program in the same column from being disturbed by reducing and excluding the sensitivity to excessive erase to selectively erase only one row at a time.

CONSTITUTION: A cell 11 consists of a drain D, a source S, a gate 12, and a floating gate 13. An erase node 36 is connected to column erase lines 26, 27, and 28 by a transistor TR 37 controlled by row select lines 29, 30, and 31. An erase potential 32 is applied to the erase node of each cell in a column of an array 10 through a column erase line. A sense amplifier GA detects the start of conduction of each cell and opens a TR 33 to disconnect the cell from the erase line. A specific row is selected, and the erase voltage is applied to only the selected erase line through a pull-up impedance 35.