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Title:
METHOD AND DEVICE FOR ASSISTING COMPONENT MOUNTING PROCESS DESIGNING
Document Type and Number:
Japanese Patent JP3249301
Kind Code:
B2
Abstract:

PURPOSE: To design a component mounting process in a short time through easy operation by automatically allocating the processes of components to be mounted on a wiring board.
CONSTITUTION: The device used for the component mounting process previously puts conditions required for electronic components in a process allocation table file 20 and puts electronic component discrimination information and component information corresponding to the conditions in a component information file 18 for the respective electronic components so that they correspond to each other; and discrimination information on then electronic components to be mounted on the wiring board is taken out of a design information file 14 and put in a used component discrimination information file 16, component information is read out of a component information file 18 by using discrimination information on each electronic component to be mounted as a key word, and the electronic component information is distributed to the process on the basis whether or not the component information meets the conditions. The conditions are represented as AND of requirements, which are represented as AND of elements corresponding to respective items of a component information record and one-bit attributes added to the respective elements.


Inventors:
Seiichi Urita
Go Onda
Yumi Terasawa
Kazuki Kitamura
Application Number:
JP18963594A
Publication Date:
January 21, 2002
Filing Date:
August 11, 1994
Export Citation:
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Assignee:
富士通株式会社
株式会社ピーエフユー
International Classes:
H05K13/00; G06F17/50; (IPC1-7): G06F17/50; H05K13/00
Domestic Patent References:
JP6196899A
JP5266106A
JP4188279A
JP4240800A
JP6164189A
Attorney, Agent or Firm:
Shinkichi Matsumoto