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Patent Searching and Data


Title:
METHOD AND DEVICE FOR CONTROLLING CACHE MEMORY
Document Type and Number:
Japanese Patent JP2000040030
Kind Code:
A
Abstract:

To improve a cache hit rate by deciding to be replaced with which cache data based on the count result of the number of cache mishits at the time of a cache mishit.

An address comparator 105 compares the address of data stored in an address storing part 103 with an address transmitted from an instruction issuing part 104 and performs hit/mishit decision. A miscounter part 106-1 counts the number of times when mishit takes place in the comparator 105 and stores the number of misses in every cache line in a mistake storing part 106-2. The parts 106-1 and 106-2 are provided in these ways and are used to decide which block to be rewritten when a cache miss takes place in a load instruction. That is, when a cache mishit occurs, the number of cache mishit of each way is compared, the cache line data of a way that has many mishit are rewritten.


Inventors:
FUKAGAWA MASAO
Application Number:
JP20914398A
Publication Date:
February 08, 2000
Filing Date:
July 24, 1998
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F12/12; G06F12/08; (IPC1-7): G06F12/12
Attorney, Agent or Firm:
Asato Kato