PURPOSE: To access a main and an auxiliary memory in accordance with processing results by the 1st and 2nd processors, to find desired data immediately when the 1st processor executes instruction, and to shorten the processing time, by providing the 1st and 2nd processors.
CONSTITUTION: The 1st memory 1, 1st processor 3, 1st channel controller 4, and a processor interface module 6 are connected to a memory bus 2, and a computer 7 provided with the 2nd processor 73 and 2nd memory 71 is connected to the module 6. Simultaneously with the execution start of a program including data operation instructions, data in an auxiliary memory 5 that the instructions require are transferred through a multiaccess controller 8 and a controller 4 to prescribed locations in the memory 1 before the operation instructions are executed. Then, the processor 73 preprocesses the information stored in the memory 71 and the processor 3 is informed of the operation instructions transmitted from the controller 8 to the memory 1, thus shortening the processing time of instructions of the processor 3.
TAKEZAWA KUNIO
SAKUGI TSUYOSHI
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