PURPOSE: To shorten the waiting time of a CPU by controlling a data transfer handshape protocol so that the final result of a pending protocol event can be defined later.

CONSTITUTION: The CPU 4 transfers data between the CPU 4 itself and an I/O channel 8 every five processor clock cycles. At the initial time of a set of five clock cycles, the CPU 4 sets data on a data bus 12 (at the time of data. reception, it is supposed that the data are put on the data bus 12) and generates a transfer request (SPU-XFR) signal. At the time of receiving a data acception(DTA-ACC) signal, the end of preceding data transfer is supposed. When a transfer completion signal is not generated, a transer inhibit signal for inhibiting the generation of a succeeding DATA-ACC signal is generated, so that the CPU 4 inspects a cause of failing the completion and cancels or reexecutes the preceding data transfer.