Title:
METHOD AND DEVICE FOR DESIGNING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2004110627
Kind Code:
A
Abstract:
To facilitate layout verification of a circuit in which an analog circuit and a digital circuit coexists.
Wiring as a possible noise source and wiring which is not noise-resistant are specified on a circuit diagram are indicated on a circuit, and an identification display means 11 identifies a pair of wiring patterns the parasitic capacity of which exceeds a specific value and displays it on the circuit diagram and a layout diagram when the parasitic capacity between the wiring patterns as the possible noise source and the wiring which is not noise-resistant is extracted.
Inventors:
MARUO AKIO
NISHIMOTO MINEO
OTAKE HIROAKI
NISHIMOTO MINEO
OTAKE HIROAKI
Application Number:
JP2002274644A
Publication Date:
April 08, 2004
Filing Date:
September 20, 2002
Export Citation:
Assignee:
ASAHI CHEMICAL MICRO SYST
International Classes:
G06F17/50; H01L21/82; H01L21/822; H01L27/04; (IPC1-7): G06F17/50; H01L21/82; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Tetsuya Mori
Yoshiaki Naito
Cui Shu Tetsu
Yoshiaki Naito
Cui Shu Tetsu