Title:
METHOD AND DEVICE FOR DETECTING AND RECOVERING INTERFERENCE BETWEEN IRREGULAR SEQUENCE LOAD INSTRUCTION AND STORE INSTRUCTION
Document Type and Number:
Japanese Patent JP2938426
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a device that detects a fact that the memory loading operation which was executed before its preceding memory storing operation is carried out by mistake, by executing a recovery sequence based on a mapping table of an area base when an interference is detected between the operations whose sequences are already changed.
SOLUTION: This system consists of a memory subsystem 101, a data cache 102, an instruction cache 103 and a processor unit 100. The unit 100 includes an instruction queue 104, an area mapping table 105, etc. The table 105 is used to detect an irregular sequence loading operation and to track the memory area which is accessed by the irregular sequence loading operation. Then a storing operation executed to the area that is accessed by the said irregular sequence loading operation is detected, and the unit 100 is instructed to perform a recovery sequence when an interference is detected between the operations whose sequences are already changed.
Inventors:
HAIME UNBERUTO MOREENO
MAYAN MODOGIRU
MAYAN MODOGIRU
Application Number:
JP5319898A
Publication Date:
August 23, 1999
Filing Date:
March 05, 1998
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G06F9/38; (IPC1-7): G06F9/38; G06F9/38
Domestic Patent References:
| JP8314721A | ||||
| JP8234981A | ||||
| JP5143332A | ||||
| JP6214799A | ||||
| JP5298091A | ||||
| JP7160501A | ||||
| JP689174A | ||||
| JP8504977A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)