To provide a method and a device for evaluating the frequency and/or phase of a digital input signal which does not use a multiplier, having integrated logic gates.

Through a chain of a coding device (3), which determines the phase value (Ca1(i)) of an input signal (x(i)), a 1st filter (4) which generates a total phase value (Sa1(i)) by summing up phase values (Ca1(i) over a length N/B of summing-up operation as a predetermined fraction 1/B of the masured length of N phase values (Ca1(ii) and compares the phase values (Ca1(i)) with a sampling rate (fa2) for converting the sampling rate of the summed-up phase value (Sa1(i) by a factor N/B, and B-1 delay elements (15, 16; 26 to 30) which delay only one sampling cycle of the converted sampling rate (fa2.B/N), the summed-up phase value (Sa1(i)) is delayed and then differently delayed summed-up phase values (Sa1(i)) are added or subtracted.