To realize certain operation verification simulation by accelerating overall (integral) operation verification simulation and preventing the simulation information from being lost.

A CPU model part 203 is set in a stand-by state by a model operation setting part 205 in a prescribed timing (address value) after an I/O model part 204 is started to operate so that simulation can be omitted under the control of a simulation control part 201. Then, the CPU model part 203 is returned to the operating state by the model operation setting part 205 after event notice including an interrupt from the I/O model part 204 is recognized by the mode operation setting part 205 so that the simulation is resumed. Thus, when any loop which is meaningless in terms of processing is being processed by the CPU model part 203 in the interrupt stand-by state from the I/O model part 204, the simulation of the CPU model part 203 is omitted.