METHOD AND DEVICE FOR FLATTENING SEMICONDUCTOR DEVICE

Title:

METHOD AND DEVICE FOR FLATTENING SEMICONDUCTOR DEVICE

Document Type and Number:

Japanese Patent JP2001260001

Kind Code:

A

Abstract:

To reduce the scratch density on the polishing surface in a polishing process.

The device for flattening a semiconductor device is provided with a dressing rate measuring device 11 for detecting the dressing rate of a polishing pad to be changed with the progress of polishing, and a surface shape measuring device 10 for measuring the surface state of the polishing pad. Torque for a polishing surface plate and driving torque for a dresser are found by converting values of current flowing to respective motors 7, 9 by an A/D converter 13, and the dressing condition is controlled by using the data automatically measured in real time so that the dressing rate having a serious effect on the scratch density may be within the range of a control specified value previously found and stored in a data base 15.

Inventors:

NISHIGUCHI TAKASHI
SATO HIDEMI
KOJIMA HIROYUKI
OKAWA TETSUO

Application Number:

JP2000068508A

Publication Date:

September 25, 2001

Filing Date:

March 13, 2000

Export Citation:

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Assignee:

HITACHI LTD

International Classes:

B24B49/18; B24B53/017; H01L21/304; (IPC1-7): B24B37/00; B24B49/18; H01L21/304

Attorney, Agent or Firm:

Kazuko Tomita

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