METHOD AND DEVICE FOR FORMING PLANAR FIELD EFFECT TRANSISTOR WITH SOURCE AND DRAIN ON INSULATOR

Title:

METHOD AND DEVICE FOR FORMING PLANAR FIELD EFFECT TRANSISTOR WITH SOURCE AND DRAIN ON INSULATOR

Document Type and Number:

Japanese Patent JPH1174522

Kind Code:

A

Abstract:

To provide a method for manufacturing a field effect transistor with source and drain on an insulator.

A method for forming a field effect transistor includes a step for forming a first void region 11 in the outer surface of a semiconductor body 10 and a step for forming a second void region 11 which is separated from the first void region by a portion of the semiconductor body 10 in the outer surface of a semiconductor body 10. The method further includes a step for depositing a dielectric material in the first void region to form a first insulating region 16 and a step for depositing dielectric material in the second void region to form a second insulating region 16. The method further includes a step for planarizing the first and second insulating regions to define a planar surface 17. The method also includes a step for forming a conductive source region 34 overlying the first insulating region, a step for forming a conductive drain region 36 overlying the second insulating region and a step for forming a conductive gate body overlying the planar surface and spaced apart from the conductive source region and the conductive drain region.

Inventors:

CHEN IH-CHIN

Application Number:

JP37007397A

Publication Date:

March 16, 1999

Filing Date:

December 19, 1997

Export Citation:

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Assignee:

TEXAS INSTRUMENTS INC

International Classes:

H01L21/76; H01L21/31; H01L21/316; H01L21/336; H01L29/06; H01L29/78; (IPC1-7): H01L29/78; H01L21/31; H01L21/316; H01L21/76

Attorney, Agent or Firm:

Akira Asamura (3 outside)

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