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Patent Searching and Data


Title:
METHOD AND DEVICE FOR INFORMATION PROCESSING
Document Type and Number:
Japanese Patent JPS5856277
Kind Code:
A
Abstract:

PURPOSE: To give an access to a main memory or a local memory with the signal of a memory controller and to accelerate an instruction cycle, by providing the local memory which stores the program routine goup of a high frequency in use and the memory controller in addition to a CPU and the main memory.

CONSTITUTION: A CPU11 includes an arithmetic controller 21, a local memory 22, a memory controller 23 and a bus interface unit 24. The memory 22 stores the program routine group which has especially high frequency in use among the operating systems to be stored in a main memory. The controller 23 incorporates an address register, a comparator, an FF and various types of gate groups. A comparison is carried out for the set value between the address and the address register every time when the CPU11 gives an access to the main memory. Then an access is given to the memory 22 based on the result of comparison. As a result, the load of a common bus is reduced and the instruction cycle is accelerated. This can improve the system performance.


Inventors:
SATOU FUMITAKA
NAGURA KUNIHIRO
Application Number:
JP15304581A
Publication Date:
April 02, 1983
Filing Date:
September 29, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F12/08; (IPC1-7): G06F13/00; G11C9/06
Domestic Patent References:
JPS5211728A1977-01-28
Attorney, Agent or Firm:
Noriyuki Noriyuki