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Title:
METHOD AND DEVICE FOR INSPECTING INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2002190508
Kind Code:
A
Abstract:

To provide the inspection method of an integrated circuit for eliminating influence due to a large subthreshold leakage current in a low-threshold voltage transistor without changing the integrated circuit, and for easily determining the presence and absence of a defective element, and to provide the inspection device of the integrated circuit.

For temperature characteristics in the subthreshold leakage current of an NMOS transistor, the leakage current can be restrained by a large amount to 96 picoamperes by decreasing room temperature to 77K, even if the transistor has a large leakage current of 3.6 microampares at a room temperature of 277K. An inspection stage 10 with cooling mechanisms utilizes the principle of a heat pipe, and comprises a refrigerant well 11, a pipe 12, a sample stage 13, and a pump 14. In this case, liquid nitrogen is used as the refrigerant, thus setting the temperature in the sample rest 13 to 77K. Also, the sample rest 13 is placed inside a vacuum chamber, thus avoiding freezing and condensation of a sample.


Inventors:
TERAO NORIYUKI
Application Number:
JP2000386513A
Publication Date:
July 05, 2002
Filing Date:
December 20, 2000
Export Citation:
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Assignee:
RICOH KK
International Classes:
G01R31/28; H01L21/66; H01L21/822; H01L27/04; G01R31/26; (IPC1-7): H01L21/66; G01R31/26; G01R31/28; H01L27/04; H01L21/822