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Title:
METHOD AND DEVICE FOR LOGIC DESIGN
Document Type and Number:
Japanese Patent JPH03242765
Kind Code:
A
Abstract:

PURPOSE: To shorten the design time by preliminarily obtaining combinations of logic circuits counter to a restriction condition and using the other combinations of logic circuits to connect logic blocks.

CONSTITUTION: Before actual connection of logic blocks 1 to N, plural kinds of logic circuit which can constituted by logic blocks 1 to N are obtained, and restriction information 7 is referred to preliminarily obtain combinations of logic circuits which are counter to the restriction condition at the time of connecting the logic blocks, and the other combinations of logic circuits are used to connect the logic blocks. Truth information is divided into several longic blocks in this manner to generate logic circuits satisfying the restriction condition of timing or the like in each logic block, and thereafter, logic blocks are connected to generate an overall logic circuit. Thus, it is sufficient if only a pertinent logic block is corrected at the time of correction after circuit design, and this device can easily and quickly cope with the increase of the overall circuit scale.


Inventors:
SAITO TOSHIKO
TOTSUGI KEISUKE
HAMADA KANMAN
Application Number:
JP3837490A
Publication Date:
October 29, 1991
Filing Date:
February 21, 1990
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Masami Akimoto



 
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