Title:
METHOD AND DEVICE FOR MONITORING AUTOMATION TEST FOR ELECTRONIC CIRCUIT
Document Type and Number:
Japanese Patent JPS60100066
Kind Code:
A
Abstract:
Circuitry required in an automatic digital integrated circuit tester to control the application of timed data pulses to the inputs to the device under test, the circuitry to generate strobe signals to control comparators connected to the outputs of the device under test, and the circuitry to decode error signals is implemented in a completely flexible, programmable architecture on a single emitter coupled logic gate array integrated circuit. Each such formatter circuit can control two device under test pins. Every possible critical signal path to the device under test is routed over a separate signal line which allows each signal path having a different propagation delay to be aligned in time by a deskewing system in order to minimize timing errors. Signals that control the driver circuits that apply data to the device under test inputs pins are separated into a SET signal line and a RESET signal line, due to the difference in propagation delay for the driver when driving the device under test input high versus driving it low. Similarly, the strobe signals to the comparators connected to the device under test output pins are separated into a high level strobe and a low level strobe, due to the difference in propagation delay for the comparator when comparing the device under test output to a high level reference versus a low level reference. The device under test input transitions and output strobes are not fixed in time with respect to the system clock, but are referenced to it which allows the drive data cycles and the compare data cycles to be somewhat independent of the sytem clock, permitting them to overlap and cross test period boundaries without requiring test vectors to be charged. The error correlator decodes the error signals produced by incorrect device under test outputs. Using timing signals derived from the clocks used to control the drive data for the device under test inputs, and the clocks used to generate strobes to control the comparators, the error correlator correctly decodes error signals and logs them in the compare memory location corresponding to the proper test vector.
Inventors:
JIYON SHINABETSUKU
Application Number:
JP16275284A
Publication Date:
June 03, 1985
Filing Date:
August 01, 1984
Export Citation:
Assignee:
FAIRCHILD CAMERA INSTR CO
International Classes:
G01R31/317; G01R31/28; G01R31/319; G01R31/3193; G06F11/22; G11C7/22; H03K5/13; H03K5/14; H03K5/00; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Kazuo Kobashi