PURPOSE: To inexpensively synchronize plural nodes at the OFF of a cache in a bus non-shared type parallel processing system having shared distributed memories.
CONSTITUTION: A mechanism for recording a node having executed an LR(load reserve) instruction, a mechanism for detecting the execution of the LR instruction and the writing of the instruction in a memory, a mechanism for emulating the writing in the memory, and a mechanism for multicasting the write in the memory about the node having executed the LR instruction which are used for synchronism at the OFF of the cache are shared with a directory 152 for recording a node caching its own memory, a bus monitoring device 151 for detecting a memory access and a mechanism for executing communication for cache consistency holding operation which are used for cache maintenance at the ON of the cache.
HAMAGUCHI KAZUMASA
FUKUI TOSHIYUKI
