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Title:
METHOD AND DEVICE FOR REDUCING DATA ERROR INDUCED BY RADIATION AND CROSSTALK
Document Type and Number:
Japanese Patent JP2011050047
Kind Code:
A
Abstract:

To provide an integrated circuit including any number of latches and filters.

Each of any number of latches 114 has a plurality of inputs 122 and 124 and a plurality of storage nodes 126 and 128. The plurality of storage nodes 126 and 128 include any number of circuit node pairs 130 forming any number of upsettable circuit node pairs 130. Each of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each of any number of filters 112 has an input and a plurality of outputs 118 and 120. Each of the plurality of outputs 118 and 120 is connected to a corresponding input of the plurality of inputs of a latch in any number of latches. Each of any number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in any number of latches 114.


Inventors:
CABANAS-HOLMEN MANUEL F
CANNON ETHAN
RABAA SALIM A
Application Number:
JP2010167649A
Publication Date:
March 10, 2011
Filing Date:
July 27, 2010
Export Citation:
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Assignee:
BOEING CO
International Classes:
H03K3/356; H03K3/3562
Domestic Patent References:
JP2007082206A2007-03-29
JP2007166066A2007-06-28
JP2006339355A2006-12-14
JP2002185309A2002-06-28
JP2007082206A2007-03-29
JP2007166066A2007-06-28
JP2006339355A2006-12-14
Other References:
JPN6015009844; Ｓａｎａ　Ｒｅｚｇｕｉ，Ｊ．Ｊ．Ｗａｎｇ，Ｅｒｉｃ　Ｃｈａｎ　Ｔｕｎｇ，Ｂｒｉａｎ　Ｃｒｏｎｑｕｉｓ: '"Ｎｅｗ　Ｍｅｔｈｏｄｏｌｏｇｉｅｓ　ｆｏｒ　ＳＥＴ　Ｃｈａｒａｃｔｅｒｉｚａｔｉｏｎ　ａｎｄ　Ｍｉ' ＩＥＥＥ　ＴＲＡＮＳＡＣＴＩＯＮＳ　ＯＮ　ＮＵＣＬＥＡＲ　ＳＣＩＥＮＣＥ ＶＯＬ．５４，ＮＯ．６, 200712, ｐｐ．２５１２-２５２４, ＩＥＥＥ
Attorney, Agent or Firm:
Sonoda Yoshitaka
Kobayashi Yoshinori



 
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