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Title:
METHOD AND DEVICE FOR SIMULATING SHAPE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND COMPUTER-READABLE RECORD MEDIUM STORED WITH SHAPE SIMULATION PROGRAM
Document Type and Number:
Japanese Patent JPH11111717
Kind Code:
A
Abstract:

To improve the accuracy of two-dimensional shape simulation of a reflow process by adding the data of Material components moving from the depth direction of an analysis segment.

The two-dimensional shape of a semiconductor integrated circuit is simulated by taking a pseudo-three-dimensional effect into consideration, in such a way that segments are arranged at prescribed intervals in the horizontal and vertical directions of an analysis segment (S200) and the higher surface heights of the intersections of the segments obtained as a result of two-dimensional shape calculation performed on each segment before reflow are held as initial values. Then reflow shape calculation is performed on each segment in the vertical and horizontal directions at finely divided reflow times (S500) and the held surface heights are updated whenever the reflow shape calculation is performed. Thereafter, the two-dimensional cross-sectional shape of the analysis segment is calculated.


Inventors:
NAKAUCHI TAKAHIRO
Application Number:
JP27021497A
Publication Date:
April 23, 1999
Filing Date:
October 02, 1997
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L23/522; H01L21/00; H01L21/316; H01L21/768; (IPC1-7): H01L21/316; H01L21/00; H01L21/768
Attorney, Agent or Firm:
Hidekazu Miyoshi (3 outside)