Title:
METHOD AND DEVICE FOR SWITCHING ADDRESS COUNTER CLOCK
Document Type and Number:
Japanese Patent JPH03240143
Kind Code:
A
Abstract:
PURPOSE: To reduce the circuit scale by providing an operation clock switch means which switches the operation clock of a counter in response to the clock of the input/output data to be applied to a RAM.
CONSTITUTION: An operation clock switch circuit 1 outputs an operation clock 4 to a counter 2 and switches (n) types of clocks 4 in response to the clock of the input/output data applied to a RAM 3. In other words, the circuit 1 switches the clocks 4 with change of the clock of the input/output data. An address 5 is outputted from the single counter 2 and therefore the continuous changes are kept despite the change of the clock 4. Thus the circuit scale is reduced and the access speed can be slowed down for the element of the RAM 3.
Inventors:
SUYAMA TEIJI
Application Number:
JP3536190A
Publication Date:
October 25, 1991
Filing Date:
February 16, 1990
Export Citation:
Assignee:
SHIKOKU NIPPON DENKI SOFTWARE
International Classes:
G06F12/02; G06F12/00; (IPC1-7): G06F12/02
Attorney, Agent or Firm:
Uchihara Shin
Previous Patent: Quick connector and leg pole locking mechanism using quick connector
Next Patent: VARIABLE LENGTH DATA MEMORY INTERFACE CIRCUIT
Next Patent: VARIABLE LENGTH DATA MEMORY INTERFACE CIRCUIT