Title:
METHOD AND DEVICE FOR TESTING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3251069
Kind Code:
B2
Abstract:
PURPOSE: To provide a device and a method of enabling semiconductor devices to be successively subjected to a DC test and a function test at two or more stations at the same time, so that semiconductor devices can be tested efficiently.
CONSTITUTION: A semiconductor device is usually tested through such a manner that devices D1-1 to D2-24 are subjected to a DC test and a function test at stations 1 and 2 respectively, wherein a DC test is carried out first. If it is found that the devices subjected to a DC test at either of the stations 1 and 2 are all defective, the devices are replaced, and then the new devices are subjected to a DC test, and after at least one of the devices is found non- defective, the devices are subjected to a function test at the stations 1 and 2. By this setup, devices are not subjected to a function test of long testing time at a single station, and the function tests done at stations 1 and 2 are lessened in frequencies to decrease a semiconductor device in check time.
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Inventors:
Naoki Miyake
Hiroshige Hirano
Hiroshige Hirano
Application Number:
JP27708292A
Publication Date:
January 28, 2002
Filing Date:
October 15, 1992
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/66; H01L21/82; G01R31/26; (IPC1-7): H01L21/66; G01R31/26; H01L21/82
Domestic Patent References:
| JP471247A | ||||
| JP60236240A | ||||
| JP468549A | ||||
| JP1119772A |
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)