To provide a diagnostic method capable of detecting the abnormality of a data bus in addition to the abnormality of a master and a slave.

A shift register 24 having cells of the same number of bits as that of a data bus is included in a common memory of an I/O module 2, a controller 1 shifts one bit of the shift register 24 in each fixed time and stores the stored contents of the register 24 in a shift register permanence detection part 13 and the I/O module 2 also shifts one bit of the contents of the register 24 in each fixed time and stores the contents in a shift register perpanence detection part 25. Prior to shifting operation, each of the controller 1 and the I/O module 2 compares the contents of preceding stored data with the current contents of the register 24, and when there is no change in the contents, judges the abnormality of the opposite device and outputs an error output 17 or 29.