Title:
METHOD FOR ESTIMATING POWER CONSUMPTION FOR MICROPROCESSOR
Document Type and Number:
Japanese Patent JP3494813
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To easily generate an instruction file to be used for the estimation of power consumption, and to easily estimate the power consumption of each instruction by calculating the power consumption of one instruction at the instruction cache miss and at the instruction cache hit from the power consumption in a prescribed cycle.
SOLUTION: An objective instruction for estimating power consumption is executed according to the flow of a pipe line by a microprocessor 3 equipped with an instruction cache 1 inside and a main memory 2 outside. An instruction file for the simulation of the power consumption comprises one file for repeatedly executing plural continuous objective instructions by a jump instruction. Then, a power consumption estimated value in the case of reading one instruction from the instruction cache 1 and executing it, and a power consumption estimated value at the item of reading one instruction from the main memory 2 and executing it are calculated, based on the power consumption in each prescribed cycle at the first round of execution of an instruction group.
Inventors:
Atsushi Kageshima
Application Number:
JP19045696A
Publication Date:
February 09, 2004
Filing Date:
July 19, 1996
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F1/28; G06F9/38; G06F11/24; G06F11/34; G06F12/08; G06F17/50; (IPC1-7): G06F11/34; G06F1/28; G06F9/38; G06F12/08
Domestic Patent References:
| JP4289469A | ||||
| JP573407A | ||||
| JP844788A |
Other References:
Ｃｈｉｎｇ−Ｌｏｎｇ Ｓｕ、外１名，“Ｃａｃｈｅ Ｄｅｓｉｇｎｓ ｆｏｒ Ｅｎｅｒｇｙ Ｅｆｆｉｃｉｅｎｃｙ”，Ｐｒｏｃｅｅｄｉｎｇｓ ｏｆ ｔｈｅ ２８ｔｈ Ａｎｎｕａｌ Ｈａｗａｉｉ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｃｏｎｆｅｒｅｎｃｅ ｏｎ Ｓｙｓｔｅｍ Ｓｃｉｅｎｃｅｓ，ＩＥＥＥ，平成７年，Ｖｏｌ．１，ｐ．３０６−３１５
Ｊｏｈｎ Ｂｕｎｄａ、外１名，“Ｅｎｅｒｇｙ−Ｅｆｆｉｃｉｅｎｔ Ｉｎｓｔｒｕｃｔｉｏｎ Ｓｅｔ Ａｒｃｈｉｔｅｃｔｕｒｅ ｆｏｒ ＣＭＯＳ Ｍｉｃｒｏｐｒｏｃｅｓｓｏｒｓ”，Ｐｒｏｃｅｅｄｉｎｇｓ ｏｆ ｔｈｅ ２８ｔｈ Ａｎｎｕａｌ Ｈａｗａｉｉ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｃｏｎｆｅｒｅｎｃｅ ｏｎ Ｓｙｓｔｅｍ Ｓｉｃｉｅｎｃｅｓ，ＩＥＥＥ，平成７年，Ｖｏｌ．１，ｐ．２９８−３０５
佐藤寿倫、外４名，“アーキテクチャレベル消費電力見積りシミュレータの開発”，情報処理学会研究報告，情報処理学会，平成７年，Ｖｏｌ．９５，Ｎｏ．１１９（ＡＲＣ−１１５、ＤＡ−７８），ｐ．７１−７６
Ｊｏｈｎ Ｂｕｎｄａ、外１名，“Ｅｎｅｒｇｙ−Ｅｆｆｉｃｉｅｎｔ Ｉｎｓｔｒｕｃｔｉｏｎ Ｓｅｔ Ａｒｃｈｉｔｅｃｔｕｒｅ ｆｏｒ ＣＭＯＳ Ｍｉｃｒｏｐｒｏｃｅｓｓｏｒｓ”，Ｐｒｏｃｅｅｄｉｎｇｓ ｏｆ ｔｈｅ ２８ｔｈ Ａｎｎｕａｌ Ｈａｗａｉｉ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｃｏｎｆｅｒｅｎｃｅ ｏｎ Ｓｙｓｔｅｍ Ｓｉｃｉｅｎｃｅｓ，ＩＥＥＥ，平成７年，Ｖｏｌ．１，ｐ．２９８−３０５
佐藤寿倫、外４名，“アーキテクチャレベル消費電力見積りシミュレータの開発”，情報処理学会研究報告，情報処理学会，平成７年，Ｖｏｌ．９５，Ｎｏ．１１９（ＡＲＣ−１１５、ＤＡ−７８），ｐ．７１−７６
Attorney, Agent or Firm:
Hidekazu Miyoshi