METHOD FOR EVALUATING PHASE COMPARATOR

Title:

METHOD FOR EVALUATING PHASE COMPARATOR

Document Type and Number:

Japanese Patent JP3297759

Kind Code:

B2

Abstract:

PURPOSE: To provide a method for evaluating phase comparators by which a phase comparator can be evaluated by extremely easily deciding the output state of the phase comparator in a DC sense without making any special circuit change.
CONSTITUTION: After raising the terminal voltages (a) and (c) at two input terminals to high levels, the voltage (b) is returned to the high level after once lowering the voltage (b) to a low level and again returned to the high level after once more lowered to the low level, while the voltage (a) is fixed at the high level. When the voltage (b) is in a state A, the voltage reaches another state B (output is at the low level) from the state A through states C, I, and E. When the voltage (b) is in the state B, the voltage (b) returns to the state B through states E, B, and E. In case the voltage (b) is in the state I, the voltage (b) reaches the state B through the states E, B, and E.

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Inventors:

Tetsuo Yamamoto

Application Number:

JP33666092A

Publication Date:

July 02, 2002

Filing Date:

November 24, 1992

Export Citation:

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Assignee:

ソニー株式会社

International Classes:

G01R25/00; G01R31/317; G01R35/00; H03K5/26; H03L7/089; G01R31/00; (IPC1-7): G01R31/00; G01R25/00; G01R31/317; G01R35/00; H03K5/26

Domestic Patent References:

JP4129324A
JP429412A
JP63136816A
JP61280116A

Attorney, Agent or Firm:

Kuninori Funabashi

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