To extract data while reducing the scale of a hardware by selecting a fixed clock when a delay time ΔTA satisfies a relation of 0≥ΔTA<ΔTα and allowing a phase detection circuit to generate a clock when a delay time ΔTA satisfies a relation of ΔTα≤ΔTA<ΔTβ, where ΔTα, ΔTβ are singular points of a line.

Let ΔTα, ΔTβ be singular points of a line, then a clock whose period is T and whose phase is delayed by a delay time δT1 from a start point of an outgoing transmission frame DSF transmission time is selected as an extracted clock TCK1 when a delay time ATA satisfies a relation of 0≤ΔTA<ΔTα. Then all incoming transmission frame USF(n) data are extracted by using the extracted clock TCK1. When the delay time ΔTA satisfies a relation of ΔTα≤ΔTA<ΔT/β, it is considered that distribution of data change points is resident within a range smaller than T/2, and a clock in synchronism with a phase of transmission data sent from any optional communication terminal equipment TRM among all communication terminal equipments TRM(1)- TRM(N) is detected by using the technology of the PLL or the like and the clock is used for a synchronization clock TCK2.