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Title:
METHOD OF FABRICATING MOS SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5555568
Kind Code:
A
Abstract:

PURPOSE: To provide a MOS semiconductor device having extermely low floating capacity and high speed operation by forming the bottom surface of source and drain regions in contact with an insulator.

CONSTITUTION: An N-type monocrystalline silicon layer 2 is formed on a p-type monocrystalline silicon substrate 1, and wafer formed with phosphorus glass layer 8 on a silicon substrate 5 and wafer formed with a phosphorus glass layer 8 on the layer 2 are adhered on both sides of the layer 8 in facing manner with each other. Then, porous substrate 1 is provided, and converted to oxide and removed thereform. Then, after a silicon oxide film 10 and a polycrystalline silicon layer 11 are formed, D-type regions 12, 13 are formed thereat by etching. Then, source and drain regions 12 and 13 are formed until reaching the boundary between the layer 2 and the layer 8, and an oxide film 14 is simultaneously formed to thereby form gate electrodes 15∼17.


Inventors:
IWAMURA MASAO
Application Number:
JP12879878A
Publication Date:
April 23, 1980
Filing Date:
October 19, 1978
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/8234; H01L21/02; H01L21/336; H01L21/8247; H01L27/00; H01L27/06; H01L27/12; H01L29/08; H01L29/78; H01L29/786; H01L29/788; H01L29/792; (IPC1-7): H01L27/12; H01L29/08; H01L29/78